With a tendency of convergence in various fields such as computers, communication, and broadcasting, demands on system-on-chip (SoC) devices increase rather than demands on an application specific integrated circuit (ASIC) or an application specific standard product (ASSP). In addition, development of the SoC industry is more promoted as information technology (IT) devices are miniaturized in a lightweight with high performance.
The SoC is a highly-intensive semiconductor technology in which existing complicated systems having various functions are integrated into a single chip. Various techniques have been researched and developed to implement the SoC. Particularly, a technique of interconnecting various intellectual property (IP) elements embedded in a chip has been focused as an important factor.
In general, a bus-based interconnection type is employed to interconnect the IP elements. However, as chips are highly integrated, and the amount of information transmitted between the IP elements sharply increases, it is thought that the bus-based SoC reaches its structural limitation.
In order to overcome such a structural limitation of the bus-based SoC, a network-on-chip (NoC) technology has been proposed to interconnect the IP elements by applying a typical network scheme to a chip structure.
The NoC technology proposes a network type on-chip interconnect (OCI) scheme to overcome a structural limitation of the existing bus-based scheme. In this NoC scheme, it is possible to implement a high-speed SOC with high performance and a low power consumption.
In the NoC scheme of the related art, an error correction code or an error correction circuit is employed for correcting an error that may be generated in data transmission/receiving. In this way, an error bit that may be generated in data transmission/receiving is checked using the error correction code or circuit, and its result is output as a single bit for correction.
In order to ensure reliability in the error check of large capacity data transmission using the NoC element of the related art, an error correction circuit having a high error correction capability using a plurality of error check bits is demanded. If such an error correction circuit having a high error correction capability is provided, the entire SoC element becomes heavy, and its power consumption also increases.
On the contrary, the power consumption may be reduced if the error correction circuit has a low error correction capability. However, its reliability is not guaranteed relatively.